1. Field of the Invention
The present invention relates to package structures, and more particularly, to a package structure having at least an electronic element and a fabrication method thereof.
2. Description of Related Art
Along with the progress of electronic industries, electronic products are developed toward the trend of miniaturization and multi-function. Accordingly, various package types have been developed. To meet the demands of semiconductor devices for high integration, miniaturization and high electrical performance, package on package (PoP) technologies are continuously improved and 3D IC stacking technologies are developed.
FIGS. 1A to 1G are schematic cross-sectional views showing a method for fabricating a package structure 1 according to the prior art.
Referring to FIG. 1A, a first carrier 10 and a chip 11 are provided. The first carrier 10 has a release layer 100. The chip 11 has an active surface 11a with a plurality of electrode pads 110 and an inactive surface 11b opposite to the active surface 11a. The semiconductor chip 11 is disposed on the release layer 100 of the first carrier 10 through the active surface 11a thereof.
Referring to FIG. 1B, by performing a molding process, an encapsulant 12 is formed on the first carrier 10 so as to encapsulate the chip 11.
Referring to FIG. 1C, the first carrier 10 is removed, and a second carrier 10′ is disposed on the inactive surface 11b of the chip 11 through a release layer 101 thereof.
Referring to FIG. 1D, a circuit structure 13 is formed on the active surface 11a of the chip 11 and electrically connected to the electrode pads 110. The circuit structure 13 has at least a dielectric layer 130, a circuit layer 131 formed on the dielectric layer 130 and electrically connected to the electrode pads 110, and a plurality of conductive vias 132 formed in the dielectric layer 130 and electrically connected to the circuit layer 131. Further, a UBM (Under Bump Metallurgy) layer 134 is formed on the outermost circuit layer 131
Referring to FIG. 1E, the second carrier 10′ is removed, and a third carrier 10″ is disposed on the circuit structure 13 through a release layer 102 thereof.
Referring to FIG. 1F, a dielectric layer 17 is formed on the encapsulant 12 and the inactive surface 11b of the chip 11. Then, a plurality of through holes are formed in the encapsulant 12 by laser and a plurality of conductors 16 are formed in the through holes of the encapsulant 12. Further, a circuit layer 18 is formed on the dielectric layer 17 and electrically connected to the conductors 16. Thereafter, an insulating layer 17′ is formed on the dielectric layer 17 and has a plurality of openings 170 exposing portions of the circuit layer 18.
Referring to FIG. 1G, the third carrier 10″ is removed, and a plurality of solder balls 19 are formed on the UBM layer 134.
However, in the above-described method of the package structure 1, the use of the first, second and third carriers 10, 10′, 10″ complicates the fabrication process and increases the material cost.
Further, since the first carrier 10 can only be removed after the encapsulant 12 is cured, the fabrication time and cost are increased.
Furthermore, after the first carrier 10 is removed, warpage easily occurs to the encapsulant 12, thus reducing the reliability of the package structure 1.
In addition, since the encapsulant 12 is made of a granular compound material, the through holes of the encapsulant 12 may be formed with uneven wall surfaces, thereby adversely affecting integrity of the conductors 16 and degrading the electrical performance.
Therefore, how to overcome the above-described drawbacks has become critical.